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Suprovab Mandal
Добавлен 25 сен 2011
Schematic to Layout Design Flow in Cadence Virtuoso
This video will guide you to how to do circuit design in Cadence Virtuoso schematic and making its layout.
Просмотров: 52 773
Добавлен 25 сен 2011
Check out full playlist link for Digital IC videos using cadence ruclips.net/p/PLRQdEiVtIUAd_yPydulrdS9qwpuBreOZE
How can i get Reg ID ?
Which Reg ID you're asking about ? 🤔
Due to COVID19 Pandemic colleges are not opening and I can't access the cadence software so I searched for an open source software and I found GLADE. Check out my playlist on Layout Designing using GLADE. #LearnFromHome Playlist Link:- ruclips.net/p/PLWcG9vtrFH0YVZvd3yf2Xmm_Gl0y-XXz6 Video 1: All the CMOS Design Rules are explained. Video 1 link: ruclips.net/video/b3IlK1WZIHA/видео.html Video 2&3: Glade Downloading, Setup and Configuration. Video 2 link: ruclips.net/video/LMZ3O6Akfro/видео.html Video 3 link: ruclips.net/video/1ueSinMmqkA/видео.html Video 4: Designing Layout of nMOS and pMOS is explained. Video 4 link: ruclips.net/video/oOblwp65WFA/видео.html Video 5: Designing CMOS Inverter Layout using 1 metal layer is explained in detail. Video 5 link: ruclips.net/video/Qr0nTPo-Ri0/видео.html Video 6: Verification of Designed Inverter Layout using LT Spice. Video 6 link: ruclips.net/video/kvrF6Zv6Y_U/видео.html Video 7: Designing CMOS Inverter Layout by using 2 metal layers and Vias. Video 7 link: ruclips.net/video/HZopqROB2GA/видео.html Video 8: Designing 2 Input CMOS NAND Gate. Video 8 link: ruclips.net/video/41067AYX_do/видео.html Video 9: Verification of Designed NAND Gate Layout using LT Spice. Video 9 link: ruclips.net/video/3pufZ6InuHQ/видео.html Video 10: Designing 2 Input CMOS NOR Gate. Video 10 link: ruclips.net/video/skYC2UnJgQ4/видео.html Kindly Like, Share among your engineering friends so that they can also learn from home and subscribe to my Channel for more GLADE Tutorials. Your Support will be appreciated. Thank You
struggle with learning this at university. thank you, your video is exacly what i need !
wait at 1:01:18 why my tool does not generate layers? there only the pin. my instructor document me to draw myself the layers. its pretty hard :(
Hello my friend, do you know how to copy relative?
Can you please tell how to check power consumption when using AC analysis?
Can you give me the download link of the libraries? Actuator I need UMC_18_CMOS library. It will be helpful for me if you give the direct download link of the library.
Hi Mandal, I'm using windows-10 64-bit .Is it possible to invoke the cadence tool in my system ?? could you guide me while installing the application if i get any errors.
Can you please give a brief explanation how to calculate W/L for the transistor size on the video?
hi bro i'm vijay final student can you give some link to download the software for practices.i'm waiting for your response.
That was great Suprovab!
Thanks :)
good work can u plz provide me detailed description & Keyboard shortcuts it is very difficult to allign etc
Hello Sir, Thanks for your video, How can I download your instructions?
Olivier Lettr Thanks for your interest Olivier. But currently I don't have the instruction set with me. Sorry for that. I will try to get that from my lab. If I can get then definitely I'll share it with you. 😇
sir .how to get this software please tell us
Gaurav kumar This software is available from Cadence. It is available in 2 editions, student and industry. If you want to have this then you have to buy this software. You can buy this from Cadence official website.
Hai Suprovab Mandal, Can we draw layout for pnp transistor in cadence or else can we automatically generate layout from schematic that containing a pnp transistor
In analog circuit, for gate to gate connection polysilicon is avoided as it has high resistance. Kindly suggest then what can be used for gate to gate connection in analog circuit
SIR, i wana to draw layout of vlsi on chip interconnect, kindly suggest how to proceed
Great Mandal
Thank you sooo much Sir...
@@SuprovabMandal hi I need your help please tell me zener diode parameters in analoglib in cadence tool
How did your transistors appeared in "pairs" after the "Generate All From Source" ??
Hi KaftiBrizola, If you consider the NAND Gate schematic, then you can observe that both the PMOSs are shared a common connection point i.e. VDD and Drain and same for NMOSs also which share the common connection point i.e. one Drain and one Source. As a result when you are using "Generate All From Source", in the layout window the transistors will appear in pair only if they have shared any common point. Rest of the connection point you have to manually connect. Hope this will help you. I'll be glad to hear from you if you face any difficulty.
Wow thank you for the quick response did not expect that! I've got exactly the same schematic with yours with the exception that I have connected the Body of the first n-MOS with its Source (On your schematic the NM0 transistor), but I don't think that it makes any difference in the layout. When I do the Generate All From Source, there are 4 separate transistors. The two differences I can see is that we have different versions of Virtuoso (I have 6.1.6 and I saw you have 6.1.5) and that I use another Library for the transistor selection(which uses 65nm technology). Thank you again for the help!
can you tell me how to find operating frequency of a transistor.
+tham Operating frequency of a transistor basically depends on your circuit's operating frequency. It can be in Hz or may be in GHz. So my advice will be please refer your circuit's operating principle.